2006 · 10 citations · 3 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice ModelingDevice ScalingIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit FabricationThin-film TransistorsCompatibility Of New MaterialsDevice OptimizationGate Oxide ScalingGate OxidesPower DensityPower Density ScalingTechnology ScalingTransistor Scaling
With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implementation into 90 and 65 nm SOI logic technologies: Transistor parameter fluctuation and pattern effects, power density limitations and the impact on the reliability of ultra-thin gate oxides, compatibility with new materials such as SiGe, transistor scaling and performance enhancement
3
Layout impact on the performance of a locally strained PMOSFET
S. Eneman, Peter Verheyen, R. Rooyackers et al. · 2005 · 44 citations
Issues and optimization of millisecond anneal process for 45 nm node and beyond
K. Adachi, K. Ohuchi, N. Aoki et al. · 2005 · 22 citations
Engineering, Electrical Engineering, Electronic Materials +15