IEEE Transactions on Nuclear Science · 1986 · 18 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsRadiation ProtectionSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignLow-dose Radiation EffectsRadiation HardeningTiming AnalysisVery-large-scale Integration LayoutCmos OscillatorsDiffusion LayersRadiation-hard ElectronicsRadiation-hardened Integrated CircuitsRadiation-hardening TechniquesRadiation-tolerant ElectronicsRing OscillatorsShift Registers
In order to design radiation-tolerant CMOS VLSI circuits, six different radiation-hardened structures including SOS, have been investigated utilizing 4-bit clocked CMOS static shift registers with a 5 V supply voltage. Packing density has been compared, utilizing clocked CMOS static shift register cells which have been designed using the same 2 μm design rules. Total dose radiation test results and latch-up holding voltages have been shown. Propagation delay times have also been shown, utilizing nineteen-stage CMOS ring oscillators. Based on the above results, the usefulness of thin field oxide introduced between source/drain diffusion layers and thick field oxide, combined with epitaxial or SOS substrate is discussed for use in radiation-tolerant CMOS VLSI designs.
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