Process Optimization of Radiation-Hardened CMOS Integrated Circuits

TLDR

The study discusses how observed physical dependences constrain models of traps responsible for radiation‑induced charging in SiO₂. The authors systematically investigated processing steps affecting radiation hardness of MOS devices, quantified voltage shift–parameter relationships, established a controlled baseline fabrication process for aluminum‑gate CMOS, and fabricated inverters that survive over 10⁸ rads (Si).

Abstract

The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108 rads (Si) have been fabricated. Restrictions that the observed physical dependences place upon possible models for the traps responsible for radiation-induced charging in SiO2 are discussed.