D.B. Estreich

An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process

D.B. Estreich, A. Ochoa, R.W. Dutton · 1978 · 78 citations

Engineering, Vlsi Design, Computer Architecture +17

Latch-Up Control in CMOS Integrated Circuits

A. Ochoa, W. R. Dawes, D.B. Estreich · IEEE Transactions on Nuclear Science · 1979 · 55 citations

Hardware Security, Low-power Electronics, Electrical Engineering +15

A DC technique for determining GaAs MESFET thermal resistance

D.B. Estreich · IEEE Transactions on Components Hybrids and Manufacturing Technology · 1989 · 48 citations

Electrical Engineering, Engineering, Gate Metal Resistivity +15

Modeling Latch-Up in CMOS Integrated Circuits

D.B. Estreich, R.W. Dutton · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1982 · 43 citations

Hardware Security, Latch-up Threshold Prediction, Electrical Engineering +14

A manufacturing process for analog and digital gallium arsenide integrated circuits

R.L. Van Tuyl, Vobulapuram Ramesh Kumar, D.C. D’Avanzo et al. · IEEE Transactions on Electron Devices · 1982 · 27 citations

Engineering, Electronic Design, Integrated Circuits +19