IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1982 · 45 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignDelay ModelingDevice ModelingDevice SimulationIntegrated Circuit DesignTiming ModelingCircuit SimulationCompact ModelingComplementary Metal-oxide-semiconductor SimulationLatchesMetal-oxide-semiconductor Field-effect Transistor ModelingThreshold Prediction Models
Latch-up is a common problem in CMOS integrated circuits. The modeling of latch-up with circuit simulation programs is addressed in this paper. The general features of a lumped element latch-up model are discussed along with a step-by-step approach to the component determination of the model. An example is presented to show the value of the latch-up model in latch-up threshold prediction. Finally, some latch-up control methods are discussed.
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Latch-Up in CMOS Integrated Circuits
B. L. Gregory, B.D. Shafer · IEEE Transactions on Nuclear Science · 1973 · 117 citations