Process and device related scaling considerations for polysilicon emitter bipolar transistors

Abstract

Vertical scaling of poly-Si emitter bipolar transistors is investigated based on experimental data and on one-dimensional device simulation. Emitter junction depths of 30 to 50 nm with excellent device characteristics are demonstrated and base widths around 50 nm are shown to be achievable on the basis of well proven processing techniques. It is shown that forward transit times around 3 ps corresponding to about 50 GHz transit frequency can be expected for such devices. An important result for these very shallow emitter base structures is that emitter and base charge storage contribute comparable amounts to the total forward transit time.