Assembly process integration challenges and reliability assessment of multiple 28nm FPGAs assembled on a Large 65nm passive interposer

Abstract

Stacked die packaging has been gaining traction in recent years due to cost and manufacturing issues associated transistor scaling. 3D die stacking architecture with through silicon vias offers a unique combination of low power and high bandwidth per watt without increasing the cost significantly. For Xilinx's FPGAs (Field Programmable Gate Array), due to its repetitive and unique structures, Stacked Silicon Integration (SSI) technology becomes a perfect fit to provide a cost effective solution to build large programmable logic devices with very high logic cell count. In the current configuration, four separate 28nm FPGA die were connected to each other through a 65nm passive silicon interposer. Arrays of more than 10k micro-bumps (ubumps) stitched these four dies together through the silicon interposer. This paper describes the technical and reliability challenges associated with 3D integration of 100um thin interposer and FPGA die on to a single package.