Post-placement Thermal Via Planning for 3D Integrated Circuit

Abstract

The 3-dimensional (3D) ICs' increased module density exacerbates the thermal hot-spot problem: a larger module packed into a smaller footprint produces a higher maximum temperature. Because of the significant impact of thermal via on lowering the thermal resistance of the chip, an appropriate thermal via planning can be hoped to alleviate the unfavorable thermal phenomena of 3D ICs. In this paper, after an iterative placement process driven by the thermal-aware gravity algorithm, we adjust iteratively the thermal via density in the specified thermal via region of the chip on the basis of a finite-difference (FD) thermal model. The final simulations on the IBM-PLACE benchmarks demonstrate our algorithm can achieve the maximum and average temperature objective while minimizing the thermal via utilization in a feasible running time