Thermal via placement in 3D ICs

TLDR

Thermal issues are increasingly critical in ICs, especially in 3D ICs, and while thermal vias can reduce chip thermal resistance, they consume routing space, necessitating efficient placement algorithms. The paper aims to develop an algorithm that assigns thermal vias to optimal 3D IC regions to adjust effective thermal conductivities while minimizing via usage. The method iteratively adjusts via conductivities using finite element analysis to meet a maximum temperature target. The approach efficiently meets the temperature goal while reducing thermal via usage.

Abstract

As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the thermal resistance of the chip itself. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional 2D ICs. In this paper, thermal vias are assigned to specific areas of a 3D IC and used to adjust their effective thermal conductivities. The thermal via placement method makes iterative adjustments to these thermal conductivities in order to achieve a desired maximum temperature objective. Finite element analysis (FEA) is used in formulating the method and in calculating temperatures quickly during each iteration. As a result, the method efficiently achieves its thermal objective while minimizing the thermal via utilization.