Concepedia

Via Optimization

Via Optimization is a physical design methodology in the context of routing within Very-Large-Scale Integration (VLSI) layout that specifically addresses the minimization and strategic placement of vias to enhance circuit performance, reliability, and manufacturability while reducing interconnect parasitics and fabrication complexity.

140

Publications

4.9K

Citations

478

Authors

138

Institutions

Publications per year

2017–2026

14

Parents

Publications

140

Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

A. Heryanto, Wahyuaji Narottama Putra, A. Trigg et al. · Journal of Electronic Materials · 2012 · 165 citations

, , +9

A New Symbolic Channel Router: YACR2

J. B. Reed, Alberto Sangiovanni‐Vincentelli, M. Santomauro · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1985 · 163 citations

, , +13

Placement and Routing in 3D Integrated Circuits

Cristinel Ababei, Yan Feng, Brent Goplen et al. · IEEE Design & Test of Computers · 2005 · 160 citations

, , +16

The X architecture

Steven Teig · 2002 · 111 citations

, , +17

Exploring regular fabrics to optimize the performance-cost trade-off

Larry Pileggi, Herman Schmit, Andrzej J. Strojwas et al. · 2003 · 111 citations

, , +15

1–5 of 140

Authors

478

  1. CK
    Cheng‐Kok Koh

    Purdue University West Lafayette, United States

    5 publications · 171 citations

    5

    h-index

  2. JC
    Jason Cong

    University of California, Los Angeles, United States

    4 publications · 61 citations

    4

    h-index

  3. TW
    Ting-Chi Wang

    National Tsing Hua University, Taiwan

    4 publications · 88 citations

    4

    h-index

  4. XH
    Xianlong Hong

    Tsinghua University, China

    4 publications · 126 citations

    4

    h-index

  5. KL
    Kuang‐Yao Lee

    National Tsing Hua University, Taiwan

    4 publications · 88 citations

    4

    h-index

1–5 of 478

Institutions

138

  1. National Taiwan University

    Taipei, Taiwan

    11 h-index

    26 publications

    725 citations

  2. Intel (United States)

    Santa Clara, United States

    8 h-index

    11 publications

    334 citations

  3. University of California, Los Angeles

    Los Angeles, United States

    6 h-index

    10 publications

    368 citations

  4. Purdue University West Lafayette

    West Lafayette, United States

    6 h-index

    7 publications

    208 citations

  5. Tsinghua University

    Beijing, China

    5 h-index

    22 publications

    668 citations

  6. IBM (United States)

    Armonk, United States

    5 h-index

    19 publications

    512 citations

  7. University of California, Berkeley

    Berkeley, United States

    5 h-index

    10 publications

    627 citations

  8. The University of Texas at Austin

    Austin, United States

    5 h-index

    15 publications

    340 citations

1–8 of 138

Venues

  1. 15

    h-index

  2. Journal of The Electrochemical Society

    JES · 4 publications · 202 citations

    4

    h-index

  3. Design Automation Conference

    Conference · 4 publications · 126 citations

    4

    h-index

  4. Asia and South Pacific Design Automation Conference

    Conference · 3 publications · 38 citations

    3

    h-index

  5. 3

    h-index

1–5