Placement and Routing in 3D Integrated Circuits

TLDR

Three‑dimensional technologies promise significant improvements in overall circuit performance. This article reviews placement and routing methods for FPGA‑ and ASIC‑style designs to exploit the flexibilities of 3D ICs. The authors describe CAD techniques that use a two‑step optimization for FPGA placement to minimize inter‑tier vias and a cost‑function weighting strategy for ASIC routing to discourage inter‑tier crossings.

Abstract

Three-dimension technologies offer great promise in providing improvements in the overall circuit performance. Physical design plays a major role in the ability to exploit the flexibilities offered in the third dimension, and this article gives an overview of placement and routing methods for FPGA- and ASIC-style designs. We describe CAD techniques for placement and routing in 3D ICs, developed under our 3D analysis and design optimization framework. These approaches address a dichotomy of design styles, both FPGA and ASIC. The factors that are important in each style are different, so that a one-size-fits-all approach is impractical, and therefore, we present separate approaches for 3D physical design for each of these technologies. Hence, our FPGA placement method uses a two-step optimization process that minimizes inter-tier vias first, followed by further optimization within and across tiers. In contrast, the ASIC flow uses cost function weighting to discourage, but not minimize, inter-tier crossings.