Via Planning
Via Planning is a methodological framework in interconnect design that systematically determines the placement, distribution, and configuration of vias to optimize electrical performance, manufacturability, and reliability within multilayer electronic systems.
19
Publications
934
Citations
53
Authors
19
Institutions
Publications per year
2017–2026
1
Parents
19
Thermal-driven multilevel routing for 3-D ICs
Jason Cong, Yan Zhang · 2005 · 153 citations
Thermal via planning for 3-D ICs
Yan Zhang · 2005 · 141 citations
3D Floorplanning with Thermal Vias
Eric T. Wong, Sung Kyu Lim · 2006 · 90 citations
1–5 of 19
53
5
h-index
4
h-index
4
h-index
3
h-index
3
h-index
1–5 of 53
19
Tsinghua University
Beijing, China
7 h-index
26 publications
796 citations
University of California San Diego
San Diego, United States
4 h-index
10 publications
230 citations
Georgia Institute of Technology
Atlanta, United States
3 h-index
6 publications
280 citations
University of California, Los Angeles
Los Angeles, United States
3 h-index
5 publications
380 citations
Intel (United States)
Santa Clara, United States
2 h-index
4 publications
188 citations
Mentor Technologies
Tulsa, United States
1 h-index
1 publications
11 citations
The University of Texas at Austin
Austin, United States
1 h-index
4 publications
44 citations
IMEC
Leuven, Belgium
1 h-index
5 publications
75 citations
1–8 of 19
Conference · 1 publications · 17 citations
1
h-index
1 publications · 79 citations
1
h-index
Conference · 1 publications · 105 citations
1
h-index
Conference · 1 publications · 44 citations
1
h-index
1 publications · 38 citations
1
h-index
1–5