Thermal-aware Layout
Thermal-Aware Layout is a VLSI layout methodology that integrates thermal management considerations into the physical design process by optimizing device placement and routing to minimize localized heat accumulation and ensure reliable circuit operation.
196
Publications
8.8K
Citations
648
Authors
196
Institutions
Publications per year
2017–2026
54
196
Computer-Aided Design · 1985 · 931 citations
A thermal-driven floorplanning algorithm for 3D ICs
1–5 of 196
648
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h-index
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University of Illinois Urbana-Champaign, United States
4 publications · 192 citations
4
h-index
4
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4
h-index
1–5 of 648
196
Georgia Institute of Technology
Atlanta, United States
14 h-index
41 publications
1.6K citations

National Taiwan University
Taipei, Taiwan
6 h-index
12 publications
443 citations
Tsinghua University
Beijing, China
6 h-index
26 publications
692 citations

Pennsylvania State University
State College, United States
5 h-index
9 publications
219 citations

University of Minnesota
Minneapolis, United States
5 h-index
5 publications
277 citations
IBM (United States)
Armonk, United States
4 h-index
5 publications
252 citations
University of Illinois Urbana-Champaign
Urbana, United States
4 h-index
10 publications
227 citations
The University of Texas at Austin
Austin, United States
4 h-index
7 publications
485 citations
1–8 of 196
10 publications · 383 citations
10
h-index
10 publications · 944 citations
10
h-index
7 publications · 262 citations
7
h-index
7 publications · 169 citations
7
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7 publications · 211 citations
7
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1–5