Thermal-aware Layout

Thermal-Aware Layout is a VLSI layout methodology that integrates thermal management considerations into the physical design process by optimizing device placement and routing to minimize localized heat accumulation and ensure reliable circuit operation.

196

Publications

8.8K

Citations

648

Authors

196

Institutions

Publications per year

2017–2026

54

Authors

648

  1. SK
    Sung Kyu Lim

    Georgia Institute of Technology, United States

    15 publications · 539 citations

    14

    h-index

  2. SS
    Sachin S. Sapatnekar

    University of Minnesota, United States

    5 publications · 196 citations

    5

    h-index

  3. MD
    Martin D. F. Wong

    University of Illinois Urbana-Champaign, United States

    4 publications · 192 citations

    4

    h-index

  4. YX
    Yuan Xie

    Pennsylvania State University, United States

    4 publications · 89 citations

    4

    h-index

  5. MP
    Mohit Pathak

    Georgia Institute of Technology, United States

    4 publications · 86 citations

    4

    h-index

1–5 of 648

Venues

  1. Microelectronics Reliability

    10 publications · 383 citations

    10

    h-index

  2. Applied Thermal Engineering

    10 publications · 944 citations

    10

    h-index

  3. 7

    h-index

  4. Integration

    7 publications · 169 citations

    7

    h-index

  5. 7

    h-index

1–5