2003 · 36 citations · 14 references
EngineeringComputer EngineeringComputer ScienceDesign AutomationDesign OptimizationOptimizationBuilt-in Self-testDesign For TestabilityMemory Subsystem DesignProcessor Core DesignTiming AnalysisConstraintsCore SystemsDesign For ScanabilityDeterministic Test Pattern GenerationEmbedded System TestingEmbedded TestPseudo-random Pattern GenerationTest Minimization
This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper, we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.
14
A distributed BIST control scheme for complex VLSI devices
Y. Zorian · 2002 · 543 citations
Engineering, Computer Engineering, Electrical Engineering +12
Testing embedded-core based system chips
Y. Zorian, Erik Jan Marinissen, S. Dey · 2002 · 427 citations
Engineering, Computer Engineering, Electrical Engineering +15
Testing ICs: getting to the core of the problem
B.T. Murray, John P. Hayes · Computer · 1996 · 96 citations
Engineering, Computer Engineering, Electrical Engineering +16