The impact of la-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress conditions

Abstract

La-doped HfSiO samples show lower threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and gate current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</sub> ), which is attributed to dipole formation at the high-k/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. At low and intermediate field stress, La-doped devices exhibit better immunity to positive bias temperature instability (PBTI) due to their lower charge trapping efficiency than the control HfSiO, which mainly results from a dipole-induced greater barrier offset. However, the primary cause for defect generation at high field stress is attributed to the La atoms in the interfacial SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer. By optimizing the technique to incorporate nitrogen into the bottom interface, this high field reliability issue can be minimized while maintaining good device characteristics.