Total-Dose Radiation and Annealing Studies: Implications for Hardness Assurance Testing

Abstract

A series of experiments covering a wide range of dose rate, bias, and annealing conditions has been performed on CMOS test transistors and 2K SRAMs. These experiments, on both hardened and commercial technologies, were designed to address hardness assurance issues associated with total-dose laboratory testing. It is demonstrated that failure dose can be a complicated function of dose rate, and that a peak in the failure-dose versus dose-rate curve generally results when there is a change in failure mode. If only one failure mode exists, then the failure-dose versus doserate curve is monotonic. Implications of proposed changes in MIL-STD-883C, Method 1019.2 are examined in light of their impact on hardness assurance. Our findings support the proposed changes of (1) keeping the time between irradiation and test less than 1 hour and (2) of a more restricted range of dose rate, i.e., 100 to 300 rad(Si)/ s. In addition, it is recommended that zero volt bias be maintained on CMOS devices between irradiation and test. Finally, techniques are presented for relating total-dose hardness as measured in the laboratory to total-dose hardness in real-world space and weapon environments.