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Future perspective and scaling down roadmap for RF CMOS
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2003
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Electrical EngineeringEngineeringVlsi DesignRf SemiconductorTechnology ScalingRadio FrequencyAntennaComputer EngineeringCmos TechnologyRf Cmos TechnologyMicroelectronicsBeyond CmosRf SubsystemGate WidthRf CmosElectromagnetic CompatibilityRf Noise
The concept of future scaling-down for RF CMOS technology has been investigated in terms of f/sub T/, f/sub max/, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are key parameters, especially in sub-100 nm gate length generations.