2002 · 13 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignClock ManagementEmbedded Memory BlocksLeakage Power ReductionMemory DevicesMemory Subsystem DesignSubthreshold Circuit DesignClock TimeDelay-locked LoopsLeakage CurrentLeakage Current ReductionLeakage-aware Memory DesignSubthreshold LeakageSubthreshold Leakage ReductionSubthreshold Memory Circuits
A 204.9 mm/sup 2/ 256 Mb SDRAM has a 29 ns RAS access time and a 1ns clock access time. The SDRAM enables double-data-rate (DDR) at more than 300 Mb/s/pin, and features low-Vth and high-drivability MOSFETs combined with subthreshold leakage current suppression that reduces standby current to 200 /spl mu/A. A 64-cycle lock-in 0.1 ns resolution delay-locked-loop (DLL) is used.
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