T. Akiba

256-Mb DRAM circuit technologies for file applications

G. Kitsukawa, Masashi Horiguchi, Y. Kawajiri et al. · IEEE Journal of Solid-State Circuits · 1993 · 39 citations

Non-volatile Memory, Engineering, Emerging Memory Technology +19

A 29-ns 64-Mb DRAM with hierarchical array architecture

M. Nakamura, Tsuyoshi Takahashi, T. Akiba et al. · IEEE Journal of Solid-State Circuits · 1996 · 36 citations

Hardware Security, Electrical Engineering, Memory Architecture +11

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays

T. Kawahara, T. Sakata, K. Itoh et al. · IEEE Journal of Solid-State Circuits · 1993 · 26 citations

Pmos Transistors, Electrical Engineering, Engineering +12

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

T. Kawahara, Y. Kawajiri, G. Kitsukawa et al. · IEEE Journal of Solid-State Circuits · 1991 · 18 citations

Electrical Engineering, Access Time, Engineering +11

A charge recycle refresh for Gb-scale DRAM's in file applications

T. Kawahara, Y. Kawajiri, Masashi Horiguchi et al. · IEEE Journal of Solid-State Circuits · 1994 · 17 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15