Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

T. Kawahara, Masashi Horiguchi, Y. Kawajiri, +3

IEEE Journal of Solid-State Circuits

Low-power ElectronicsNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design +12

A 23-ns 1-Mb BiCMOS DRAM

G. Kitsukawa, Kazumasa Yanagisawa, Y. Kobayashi, +10

IEEE Journal of Solid-State Circuits

Electrical EngineeringEngineeringEmerging Memory TechnologyComputer EngineeringComputer Architecture +11

256-Mb DRAM circuit technologies for file applications

G. Kitsukawa, Masashi Horiguchi, Y. Kawajiri, +16

IEEE Journal of Solid-State Circuits

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureExperimental 256-Mb Dram +17

A 29-ns 64-Mb DRAM with hierarchical array architecture

M. Nakamura, Tsuyoshi Takahashi, T. Akiba, +9

IEEE Journal of Solid-State Circuits

Hardware SecurityElectrical EngineeringMemory ArchitectureEngineeringVlsi Design +9

An experimental 1-Mbit BiCMOS DRAM

G. Kitsukawa, R. Hori, Y. Kawajiri, +8

IEEE Journal of Solid-State Circuits

Hardware SecurityNon-volatile MemoryElectrical EngineeringChip SizeEngineering +8

Performance and structures of scaled-down bipolar devices merged with CMOSFETs

Hiroyoshi Higuchi, G. Kitsukawa, Tatsuhiko N. Ikeda, +3

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigh-speed Electronics +13

256 Mb DRAM technologies for file applications

G. Kitsukawa, Masashi Horiguchi, Y. Kawaijiri, +15

Non-volatile MemoryElectrical EngineeringEngineeringEmerging Memory TechnologyComputer Engineering +12

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays

T. Kawahara, T. Sakata, K. Itoh, +4

IEEE Journal of Solid-State Circuits

Pmos TransistorsElectrical EngineeringEngineeringVlsi DesignGigabit-scale Dram Arrays +10

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques

G. Kitsukawa, K. Itoh, R. Hori, +5

IEEE Journal of Solid-State Circuits

Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer Architecture +16

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

T. Kawahara, Y. Kawajiri, G. Kitsukawa, +7

IEEE Journal of Solid-State Circuits

Electrical EngineeringAccess TimeEngineeringVlsi DesignAddress Buffers +9