An experimental 1-Mbit BiCMOS DRAM

Abstract

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.