IEEE Journal of Solid-State Circuits · 1987 · 30 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice CharacterizationLow-power Digital Circuit DesignMemory DevicesMemory Subsystem DesignBicmos TechnologyCircuit ConfigurationComplementary Metal-oxide-semiconductor DesignComplementary Metal-oxide-semiconductor DevicesHigh-speed Circuit DesignLow-power Memory CircuitsMemory Circuit DesignPeripheral Drivers
Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.
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An experimental 1Mb DRAM with on-chip voltage limiter
K. Itoh, R. Hori, J. Etoh et al. · 1984 · 66 citations
Engineering, Computer Engineering, Electrical Engineering +15
Circuit technologies for 16Mb DRAMs
T. Mano, Takeshi Matsumura, J. Yamada et al. · 1987 · 37 citations
Engineering, Computer Engineering, Electrical Engineering +14
K. Ogiue, M. Odaka, S. Miyaoka et al. · 1986 · 24 citations
Engineering, Computer Engineering, Electrical Engineering +17