IEEE Journal of Solid-State Circuits · 1990 · 39 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyMemory DevicesMemory Subsystem DesignBicmos TechnologyBipolar Circuit DesignComplementary Metal-oxide-semiconductor DesignComplementary Metal-oxide-semiconductor DevicesMemory Circuit DesignSensingSige Bicmos DesignSpeed Characteristics
A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm/sup 2/, in spite of a 1.3- mu m lithography level.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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An Experimental 16mb Dram with Transposed Data-Line Structure
A 16mb Dram with an Open Bit-Line Architecture
An experimental 1-Mbit BiCMOS DRAM
G. Kitsukawa, R. Hori, Y. Kawajiri et al. · IEEE Journal of Solid-State Circuits · 1987 · 30 citations
Engineering, Computer Engineering, Electrical Engineering +17
An Experimental 16mb Cmos dram Chip with a 100mhz Serial Read/Write Mode
Watanabe †↑, Itoh, Sakui et al. · 1988 · 24 citations
Engineering, Computer Engineering, Electrical Engineering +14