Duty Cycle Correction

Duty Cycle Correction is a methodological technique in clock management that adjusts the proportion of time a clock signal remains active within a period to achieve a desired duty cycle, distinguishing itself from other clock synchronization methods by specifically targeting duty cycle asymmetry rather than phase or frequency alignment.

108

Publications

4K

Citations

490

Authors

122

Institutions

Publications per year

2017–2026

18

Authors

490

  1. JK
    Joongsik Kih

    Seoul National University, South Korea

    4 publications · 103 citations

    4

    h-index

  2. WY
    Won-Joo Yun

    Keio University, Japan

    4 publications · 98 citations

    4

    h-index

  3. SJ
    Seong-Jin Jang

    Samsung (South Korea), South Korea

    4 publications · 63 citations

    4

    h-index

  4. JA
    Jin-Hong Ahn

    SK Group (United States), United States

    3 publications · 65 citations

    3

    h-index

  5. JZ
    Jared Zerbe

    Rambus (United States), United States

    3 publications · 388 citations

    3

    h-index

1–5 of 490

Venues

  1. IEEE Journal of Solid-State Circuits

    13 publications · 1.5K citations

    13

    h-index

  2. 9

    h-index

  3. Electronics Letters

    7 publications · 146 citations

    7

    h-index

  4. IEEE Transactions on Power Electronics

    6 publications · 406 citations

    6

    h-index

  5. 5

    h-index

1–5