Duty Cycle Correction
Duty Cycle Correction is a methodological technique in clock management that adjusts the proportion of time a clock signal remains active within a period to achieve a desired duty cycle, distinguishing itself from other clock synchronization methods by specifically targeting duty cycle asymmetry rather than phase or frequency alignment.
108
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4K
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490
Authors
122
Institutions
Publications per year
2017–2026
18
Parents
108
Wanghua Wu, Chih-Wei Yao, Kunal Godbole et al. · IEEE Journal of Solid-State Circuits · 2019 · 192 citations
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122
Samsung (South Korea)
Seoul, South Korea
12 h-index
91 publications
1.8K citations
University of Illinois Urbana-Champaign
Urbana, United States
6 h-index
12 publications
602 citations

National Taiwan University
Taipei, Taiwan
4 h-index
8 publications
218 citations
SK Group (South Korea)
Seoul, South Korea
4 h-index
57 publications
1.2K citations
Rambus (United States)
Sunnyvale, United States
4 h-index
28 publications
3K citations
Korea University
Seoul, South Korea
3 h-index
8 publications
297 citations
SK Group (United States)
San Jose, United States
3 h-index
31 publications
834 citations
Seoul National University
Seoul, South Korea
3 h-index
12 publications
940 citations
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13 publications · 1.5K citations
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9 publications · 244 citations
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7 publications · 146 citations
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6 publications · 406 citations
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5 publications · 105 citations
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