An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Seung-Jun Bae, Kwang‐Il Park, Jeong-Don Ihm, +21

IEEE Journal of Solid-State Circuits

Mb Gddr4EngineeringVlsi DesignComputer ArchitectureIntegrated Circuits +15

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Seung-Jun Bae, Young‐Soo Sohn, Kwang‐Il Park, +23

Hardware SecuritySystem On ChipMultifaceted ClockingEngineeringVlsi Design +12

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Chang‐Kyo Lee, Yoon-Joo Eom, Jin‐Hee Park, +34

Low-power ElectronicsHardware SecurityElectrical EngineeringSplit-die ArchitectureLow-power Mobile Dram +13

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Tae-Young Oh, Hoeju Chung, Young-Chul Cho, +22

Lpddr4 DramEngineeringVlsi DesignLpddr4 SdramVlsi Architecture +8

A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation

Young‐Soo Sohn, Seung-Jun Bae, Hong-June Park, +2

Cmos LadfeDfe Input BufferEngineeringVlsi DesignMixed-signal Integrated Circuit +8

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, +36

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignVlsi ArchitectureMixed-signal Integrated CircuitDram Process +12

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Tae-Young Oh, Young‐Soo Sohn, Seung-Jun Bae, +27

IEEE Journal of Solid-State Circuits

EngineeringMemory DesignVlsi DesignComputer ArchitectureGddr5 Sdram +14

CMOS digital duty cycle correction circuit for multi-phase clock

Yoonjung Jang, Seung-Jun Bae, Ha-Min Park

Electronics Letters

Electrical EngineeringFixed-delay Rising-edge OutputEngineeringAnalog-to-digital ConverterClock Recovery +9

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Seung-Jun Bae, Young‐Soo Sohn, Tae-Young Oh, +26

Hardware SecuritySystem On ChipCrosstalk EqualizerChannel Crosstalk EqualizerVlsi Design +13

A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

Seung-Jun Bae, Hyung‐Joon Chi, Hyung-Rae Kim, +1

EngineeringVlsi DesignMixed-signal Integrated CircuitEqualization SkewComputer Engineering +8