A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory

Chulbum Kim, Doo-Hyun Kim, Woopyo Jeong, +27

IEEE Journal of Solid-State Circuits

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureComputer Memory +14

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

Dongku Kang, Woopyo Jeong, Chulbum Kim, +26

IEEE Journal of Solid-State Circuits

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureIntegrated Circuits +16

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

Woopyo Jeong, Jae-Woo Im, Doo-Hyun Kim, +26

IEEE Journal of Solid-State Circuits

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer Architecture3D Memory +16

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

Dongku Kang, Woopyo Jeong, Chulbum Kim, +27

Planar NandEngineeringEmerging Memory TechnologyComputer ArchitectureAdvanced Packaging (Semiconductors) +16

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, +41

Hardware Security3D Ic ArchitectureElectrical EngineeringEngineeringNanoelectronics +13

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, +31

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureMulti-channel Memory Architecture +18

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Seung-Jun Bae, Kwang‐Il Park, Jeong-Don Ihm, +21

IEEE Journal of Solid-State Circuits

Mb Gddr4EngineeringVlsi DesignComputer ArchitectureIntegrated Circuits +15

13.4 A 512Gb 3-bit/Cell 3D 6^th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

Dongku Kang, Minsu Kim, Su Chang Jeon, +46

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

Seungjae Lee, Jin-Yub Lee, Il-Han Park, +42

Non-volatile MemoryElectrical EngineeringI/o RateEngineeringMemory Design +12

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3^rd-Generation 10nm DRAM

Yong-Hun Kim, Hyungjin Kim, Jaemin Choi, +31

Lpddr5 Sdram ApplyingHigh DensityElectrical EngineeringMobile DramEngineering +13