A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation

Abstract

A CMOS LADFE (look-ahead decision feedback equalization) receiver with a pin-to-pin time skew compensation was proposed and implemented for high-speed chip-to-chip communication such as multi-drop DRAM interface. The look-ahead scheme in DFE input buffer increased the maximum data rate from 1.4 Gbps to 2.2 Gbps. Different sampling clock was synthesized for each pin by using an /spl times/2 over-sampling scheme. Active chip area per pin is 100 /spl mu/m/spl times/800 /spl mu/m with a 2.5 V, 0.25 /spl mu/m CMOS process.