23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Abstract

With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.