Chang‐Kyo Lee

A 550-$\mu\hbox{W}$ 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction

Sang-Hyun Cho, Chang‐Kyo Lee, Jong-Kee Kwon et al. · IEEE Journal of Solid-State Circuits · 2011 · 105 citations

Engineering, Electrical Engineering, Analog Electronics +16

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Chang‐Kyo Lee, Yoon-Joo Eom, Jin‐Hee Park et al. · 2017 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm

Sang-Hyun Cho, Chang‐Kyo Lee, Sang‐Gug Lee et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2011 · 28 citations

Engineering, Computer Engineering, Electrical Engineering +17

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Hyung‐Joon Chi, Chang‐Kyo Lee, Jung Hwan Park et al. · 2020 · 26 citations

Engineering, Computer Engineering, Computer Systems +17

A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

Barosaim Sung, Chang‐Kyo Lee, Wan Kim et al. · 2013 · 25 citations

Engineering, Computer Engineering, Electrical Engineering +17