Hyung‐Joon Chi

Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces

Kyoungho Lee, Hae-Kang Jung, Hyung‐Joon Chi et al. · IEEE Transactions on Advanced Packaging · 2009 · 47 citations

Electrical Engineering, Engineering, Vlsi Design +12

A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

Seung-Jun Bae, Hyung‐Joon Chi, Hyung-Rae Kim et al. · 2005 · 29 citations

Engineering, Vlsi Design, Mixed-signal Integrated Circuit +10

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

Hyung‐Joon Chi, Jae‐Seung Lee, Seong-Hwan Jeon et al. · IEEE Journal of Solid-State Circuits · 2011 · 29 citations

Electrical Engineering, Memory Architecture, Engineering +13

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Hyung‐Joon Chi, Chang‐Kyo Lee, Jung Hwan Park et al. · 2020 · 26 citations

Non-volatile Memory, Engineering, Energy Efficiency +21

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme

Seung-Jun Bae, Hyung‐Joon Chi, Young‐Soo Sohn et al. · IEEE Journal of Solid-State Circuits · 2005 · 25 citations

Dual-loop Delay-locked Loop, Low Jitter, Vlsi Design +10