A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

Abstract

A 3Gbit/s/pin 8b parallel 4-drop single-ended DRAM transceiver is implemented in a 0.25 /spl mu/m CMOS process. Digital calibrations are performed for equalization and compensation of data skew and offset voltage. A continuously active on-die termination is used to reduce reflections. A phase detector is proposed for the digital DLL to achieve the S/H time of 10ps.