Tae-Young Oh

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Tae-Young Oh, Hoeju Chung, Junyoung Park et al. · IEEE Journal of Solid-State Circuits · 2014 · 50 citations

Engineering, Computer Engineering, Electrical Engineering +17

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Chang‐Kyo Lee, Yoon-Joo Eom, Jin‐Hee Park et al. · 2017 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +17

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Tae-Young Oh, Hoeju Chung, Young-Chul Cho et al. · 2014 · 40 citations

Engineering, Computer Engineering, Computer Science +17

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Tae-Young Oh, Young‐Soo Sohn, Seung-Jun Bae et al. · IEEE Journal of Solid-State Circuits · 2010 · 34 citations

Engineering, Computer Engineering, Embedded Systems +12

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Seung-Jun Bae, Young‐Soo Sohn, Tae-Young Oh et al. · 2011 · 32 citations

Engineering, Computer Engineering, Electrical Engineering +17