Won-Joo Yun - Concepedia

Author

Won-Joo Yun

Keio University

Also Known As

Won-Joo Yun, Won-joo Yun, Wonjoo Yun

Publications

281

Citations

H-Index

Concepts

All Affiliations

Keio University Samsung (South Korea)SK Group (South Korea)Korea University

About

Won-Joo Yun is an author at Keio University specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	227
2	Computer Engineering	8	8	227
3	Electrical Engineering	6	6	197
4	Systems Engineering	1	1	33
5	Asynchronous Circuits	1	1	33

Won-Joo Yun

Publications

237

Citations

H-Index

Page 1

	Year	Citations
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution Kyomin Sohn, Won-Joo Yun, Reum Oh, IEEE Journal of Solid-State Circuits Hardware SecurityNon-volatile MemoryElectrical EngineeringV 20Engineering	2016	60
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology Won-Joo Yun, Hyun‐Woo Lee, Dongsuk Shin, EngineeringVlsi DesignComputer ArchitectureAll-digital DllUpdate Gear Circuit	2008	33
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Electrical EngineeringLow JitterVlsi DesignEngineeringHigh-frequency Device	2010	33
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution Kyomin Sohn, Won-Joo Yun, Reum Oh, Non-volatile MemoryElectrical EngineeringEngineeringVlsi DesignHigh-performance Architecture	2016	33
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Electrical EngineeringEngineeringNon-contact Memory ModuleVlsi ArchitectureMulti-drop Bus System	2012	26
A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM Hyun-Woo Lee, Won-Joo Yun, Sin-deok Kang, X32 Gddr SdramEngineeringVlsi DesignClock RecoveryData Converter	2005	20
17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180&#x00B0; phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs Won-Joo Yun, Indal Song, Hanki Jeoung, Electrical EngineeringEngineeringAnalog-to-digital ConverterClock RecoveryData Converter	2015	12
A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Locking CyclesDie AreaEngineeringVlsi DesignClock Recovery	2013	10
A 0.17&#x2013;1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme Dongsuk Shin, Won-Joo Yun, Hyun‐Woo Lee,	2008	10

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