Won-Joo Yun

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Kyomin Sohn, Won-Joo Yun, Reum Oh et al. · IEEE Journal of Solid-State Circuits · 2016 · 60 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +13

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

Won-Joo Yun, Hyun‐Woo Lee, Dongsuk Shin et al. · 2008 · 33 citations

Engineering, Vlsi Design, Computer Architecture +16

A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology

Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2010 · 33 citations

Electrical Engineering, Low Jitter, Vlsi Design +13

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Kyomin Sohn, Won-Joo Yun, Reum Oh et al. · 2016 · 33 citations

Non-volatile Memory, Electrical Engineering, Engineering +14

A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line

Won-Joo Yun, Shinya Nakano, Wataru Mizuhara et al. · 2012 · 26 citations

Electrical Engineering, Engineering, Non-contact Memory Module +11