Reum Oh

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Kyomin Sohn, Won-Joo Yun, Reum Oh et al. · IEEE Journal of Solid-State Circuits · 2016 · 60 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +13

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Kyomin Sohn, Won-Joo Yun, Reum Oh et al. · 2016 · 33 citations

Non-volatile Memory, Electrical Engineering, Engineering +14

A snap-back suppressed shorted-anode lateral trench insulated gate bipolar transistor (LTIGBT) with insulated trench collector

Juhyun Oh, Dae Hwan Chun, Reum Oh et al. · 2011 · 21 citations

Device Modeling, Electrical Engineering, Semiconductor Device +11

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3^rd-Generation 10nm DRAM

Yong-Hun Kim, Hyungjin Kim, Jaemin Choi et al. · 2021 · 20 citations

Lpddr5 Sdram Applying, High Density, Electrical Engineering +15

DSAC: Low-Cost RowHammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm

Seungki Hong, Dongha Kim, Reum Oh et al. · arXiv (Cornell University) · 2023 · 15 citations · Full text