Yong-Hun Kim

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · IEEE Journal of Solid-State Circuits · 2018 · 39 citations

Engineering, Vlsi Design, Vlsi Architecture +14

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

Yong-Hun Kim, Young-Ju Kim, Tae‐Ho Lee et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2015 · 38 citations

Engineering, Vlsi Design, Spectrum Balancing +11

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · 2018 · 27 citations

Engineering, Hardware Acceleration, High Bandwidth Memory +13

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

Dae-Hyun Kim, Byungkyu Song, Hyun-A Ahn et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 21 citations

Artificial Intelligence, Engineering, Vlsi Design +12

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3^rd-Generation 10nm DRAM

Yong-Hun Kim, Hyungjin Kim, Jaemin Choi et al. · 2021 · 20 citations

Lpddr5 Sdram Applying, High Density, Electrical Engineering +15