Yong-Hun Kim - Concepedia

Author

Yong-Hun Kim

Korea Advanced Institute of Science and Technology ORCID

Also Known As

Feng, Y J. Kim, Yong-Hun Kim, Yonghun Kim, Yong‐Hun Kim, 인천소방본부

Publications

339

Citations

H-Index

Concepts

All Affiliations

Korea Advanced Institute of Science and Technology Samsung (South Korea)

About

Yong-Hun Kim is an author at Korea Advanced Institute of Science and Technology specializing in computer engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	196
2	Computer Engineering	9	9	201
3	Electrical Engineering	3	3	50
4	Civil Engineering	1	1	10
5	Computer Science	1	1	27

Yong-Hun Kim

Publications

250

Citations

H-Index

Page 1

	Year	Citations
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignVlsi ArchitectureMixed-signal Integrated CircuitDram Process	2018	39
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method Yong-Hun Kim, Young-Ju Kim, Tae‐Ho Lee, IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringVlsi DesignSpectrum BalancingAnalog DesignEqualizer Type	2015	38
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, EngineeringHardware AccelerationHigh Bandwidth MemoryGddr6 DramVlsi Architecture	2018	27
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process Dae-Hyun Kim, Byungkyu Song, Hyun-A Ahn, 2022 IEEE International Solid- State Circuits Conference (ISSCC) Artificial IntelligenceEngineeringVlsi DesignMobile SystemsVlsi Architecture	2022	21
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3<sup>rd</sup>-Generation 10nm DRAM Yong-Hun Kim, Hyungjin Kim, Jaemin Choi, Lpddr5 Sdram ApplyingHigh DensityElectrical EngineeringMobile DramEngineering	2021	20
An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface Yong-Hun Kim, Tae‐Ho Lee, Hyun‐Kyu Jeon, IEEE Transactions on Circuits and Systems I Regular Papers Input JitterLcd Intra-panel InterfaceData ConverterClock RecoveryAnalog Design	2017	17
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control Daewoong Lee, Dongil Lee, Yong-Hun Kim, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Low-power ElectronicsDfe Feedback DelayElectrical EngineeringEngineeringMixed-signal Integrated Circuit	2018	17
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ Daewoong Lee, Jaehyeok Baek, Hye-Jung Kwon, IEEE Journal of Solid-State Circuits	2022	16
A Robust Current Controller for Uncertain Permanent Magnet Synchronous Motors with a Performance Recovery Property for Electric Power Steering Applications Yong-Hun Kim, Hyung-Tae Seo, Seok‐Kyoon Kim, Energies Current Tracking PerformanceElectrical EngineeringElectric MachineEngineeringState Observer	2018	13
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator Tae‐Ho Lee, Yong-Hun Kim, Jaehyeong Sim, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Digital ClockEngineeringClock RecoveryData ConverterMixed-signal Integrated Circuit	2015	11

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