Hye-Jung Kwon

Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces

Kyoungho Lee, Hae-Kang Jung, Hyung‐Joon Chi et al. · IEEE Transactions on Advanced Packaging · 2009 · 47 citations

Electrical Engineering, Engineering, Vlsi Design +12

A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio

Hye-Jung Kwon, Jae-seung Lee, Jae‐Yoon Sim et al. · 2011 · 41 citations

Open-loop Architecture, Electrical Engineering, Engineering +11

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · IEEE Journal of Solid-State Circuits · 2018 · 39 citations

Engineering, Vlsi Design, Vlsi Architecture +14

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

Hye-Jung Kwon, Jae‐Seung Lee, Byungsub Kim et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2014 · 27 citations

Data Converter, Mixed-signal Integrated Circuit, Analog Design +7

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · 2018 · 27 citations

Engineering, Hardware Acceleration, High Bandwidth Memory +13