Su-Yeon Doo

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Tae-Young Oh, Hoeju Chung, Junyoung Park et al. · IEEE Journal of Solid-State Circuits · 2014 · 49 citations

Electrical Engineering, Engineering, Vlsi Design +15

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Tae-Young Oh, Hoeju Chung, Young-Chul Cho et al. · 2014 · 40 citations

Lpddr4 Dram, Engineering, Vlsi Design +10

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · IEEE Journal of Solid-State Circuits · 2018 · 39 citations

Engineering, Vlsi Design, Vlsi Architecture +14

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Seung-Jun Bae, Young‐Soo Sohn, Tae-Young Oh et al. · 2011 · 32 citations

Hardware Security, System On Chip, Crosstalk Equalizer +15

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · 2018 · 27 citations

Engineering, Hardware Acceleration, High Bandwidth Memory +13