Su-Yeon Doo - Concepedia

Author

Su-Yeon Doo

Samsung (South Korea)

Also Known As

Su-Yeon Doo

Publications

244

Citations

H-Index

Concepts

All Affiliations

Samsung (South Korea)

About

Su-Yeon Doo is an author at Samsung (South Korea) specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	244
2	Computer Engineering	8	8	244
3	Electrical Engineering	4	4	106
4	Computer Science	1	1	27
5	Systems Engineering	1	1	26

Su-Yeon Doo

Publications

244

Citations

H-Index

Page 1

	Year	Citations
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation Tae-Young Oh, Hoeju Chung, Junyoung Park, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringVlsi DesignVlsi ArchitectureGbit Lpddr4 Sdram	2014	49
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation Tae-Young Oh, Hoeju Chung, Young-Chul Cho, Lpddr4 DramEngineeringVlsi DesignLpddr4 SdramVlsi Architecture	2014	40
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignVlsi ArchitectureMixed-signal Integrated CircuitDram Process	2018	39
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW Seung-Jun Bae, Young‐Soo Sohn, Tae-Young Oh, Hardware SecuritySystem On ChipCrosstalk EqualizerChannel Crosstalk EqualizerVlsi Design	2011	32
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, EngineeringHardware AccelerationHigh Bandwidth MemoryGddr6 DramVlsi Architecture	2018	27
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process Hyung‐Joon Chi, Chang‐Kyo Lee, Jung Hwan Park, Non-volatile MemoryEngineeringEnergy EfficiencyMobile DevicesEmerging Memory Technology	2020	26
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices Hye-Jung Kwon, Eunsung Seo, Chan Yong Lee, Low-power ElectronicsHardware SecurityElectrical EngineeringNon-volatile MemoryEngineering	2017	19
A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface Seung-Jun Bae, Young‐Soo Sohn, Tae-Young Oh, Isi Reduction TechniquesElectrical EngineeringLow JitterVlsi DesignEngineering	2010	12

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