A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Abstract

Starting at 512Mb 6Gb/s/pin [1], GDDR5's speed and density have been steadily developing for about 10 years; recently achieving 8Gb 9Gb/s/pin [2] with per-pin timing training. Although 8Gb GDDR5X can operate at 12Gb/s [3] by increasing the burst length (BL) from 8 to 16, a degradation in system performance at a data granularity of 64B is seen. The I/O specification, using PLL clocking that additionally causes PLL jitter, has not changed much compared with GDDR5. To overcome these issues, GDDR6 introduced a dual channel for a data granularity of 32B with a BL16, per-bit training of l/ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</inf> , and an equalizer with PLL-less clocking. This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process.