Minsu Ahn

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · IEEE Journal of Solid-State Circuits · 2018 · 39 citations

Engineering, Vlsi Design, Vlsi Architecture +14

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · 2018 · 27 citations

Engineering, Hardware Acceleration, High Bandwidth Memory +13

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

Hye-Yoon Joo, Seung-Jun Bae, Young‐Soo Sohn et al. · 2016 · 26 citations

Hardware Security, Wck Clock Receiver, Engineering +10

Out-of-Core Remeshing of Large Polygonal Meshes

Minsu Ahn, Igor Guskov, Seungyong Lee · IEEE Transactions on Visualization and Computer Graphics · 2006 · 22 citations

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

Young-Chul Cho, Yong-Cheol Bae, Byoung-Mo Moon et al. · 2013 · 21 citations

Non-volatile Memory, Electrical Engineering, Engineering +15