Yong-Cheol Bae

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Kyomin Sohn, Won-Joo Yun, Reum Oh et al. · IEEE Journal of Solid-State Circuits · 2016 · 62 citations

Engineering, Computer Engineering, High-performance Computing +15

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Tae-Young Oh, Hoeju Chung, Junyoung Park et al. · IEEE Journal of Solid-State Circuits · 2014 · 50 citations

Engineering, Computer Engineering, Electrical Engineering +17

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Chang‐Kyo Lee, Yoon-Joo Eom, Jin‐Hee Park et al. · 2017 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee et al. · 2012 · 39 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

Young-Chul Cho, Yong-Cheol Bae, Byoung-Mo Moon et al. · 2013 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +17