IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2015 · 39 citations · 22 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingLow-power Digital Circuit DesignAdaptive EqualizationCmos Analog Circuit DesignCmos Analog Integrated CircuitsEqualizationGainPower ConsumptionPower Consumption Optimization
This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE. Thus, adaptation loops for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip consumes 34.2 mW from 1.2 V supply with 65-nm CMOS process.
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A high-efficiency CMOS voltage doubler
P. Favrat, P. Deval, M. Declercq · IEEE Journal of Solid-State Circuits · 1998 · 416 citations