A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

Abstract

Mobile systems for 5G communications and emerging technologies, such as advanced driver assistance system (ADAS), augmented reality (AR), and artificial intelligence (AI), demand high-density, high-speed, and low-power DRAM.LPDDR5 has played an important role in such systems, by offering continuous improvements in memory density (8, 12, and 16Gb) and speed (up to 8.5Gb/s) [1, 2, 3].LPDDR5X has new high-speed enabling features: per-pin DFE training, pre-emphasis for DQ driver, receiver offset calibration training, and a read duty-cycle adjuster. By employing these speed enhancement techniques, we have successfully implemented a 9.5Gb/s/pin 16Gb LPDDR5X using a fourth generation 10nm DRAM fabrication technology. This paper also presents a power-efficient LPDDR5X using (1) a non-stacking bank architecture, (2) an offset-calibrated sense amplifier for the global data lines, (3) an extended dynamic voltage and frequency scaling core (DVFSC), (4) a stacked output driver, and (5) a low-power data aligner.