Kunal Godbole

A 28-nm 75-fs_rms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Wanghua Wu, Chih-Wei Yao, Kunal Godbole et al. · IEEE Journal of Solid-State Circuits · 2019 · 183 citations

Pll Architecture, Integrated Phase Noise, Engineering +13

A 14-nm 0.14-ps_rmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Chih-Wei Yao, Ronghua Ni, Chung Lau et al. · IEEE Journal of Solid-State Circuits · 2017 · 69 citations

Fractional Spurs, Engineering, Clock Recovery +10

A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor

Alberto Cicalini, Sankaran Aniruddhan, Rahul Apte et al. · 2011 · 33 citations

Wireless Communications, Engineering, Vlsi Design +17

24.8 A 14nm fractional-N digital PLL with 0.14ps<inf>rms</inf> jitter and −78dBc fractional spur for cellular RFICs

Chih-Wei Yao, Wing Fai Loke, Ronghua Ni et al. · 2017 · 16 citations

Wireless Communications, Engineering, 5G System +14