Chih-Wei Yao

A 28-nm 75-fs_rms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Wanghua Wu, Chih-Wei Yao, Kunal Godbole et al. · IEEE Journal of Solid-State Circuits · 2019 · 183 citations

Pll Architecture, Integrated Phase Noise, Engineering +13

A 14-nm Ultra-Low Jitter Fractional-<i>N</i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

Wanghua Wu, Chih-Wei Yao, Chengkai Guo et al. · IEEE Journal of Solid-State Circuits · 2021 · 126 citations

Pll Architecture, Electrical Engineering, Engineering +13

A 14-nm 0.14-ps_rmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Chih-Wei Yao, Ronghua Ni, Chung Lau et al. · IEEE Journal of Solid-State Circuits · 2017 · 69 citations

Fractional Spurs, Engineering, Clock Recovery +10

A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW

Ashutosh Verma, Venu Bhagavatula, Amitoj Singh et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 61 citations

Wireless Communications, 5G Networks, Engineering +15

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS

Jongwoo Lee, Ki Yong Son, Hyung-sun Lim et al. · IEEE Journal of Solid-State Circuits · 2019 · 60 citations