Young-Jung Choi

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Hyun-Woo Lee, Hoon Choi, Beomju Shin et al. · IEEE Journal of Solid-State Circuits · 2012 · 26 citations

Engineering, Computer Engineering, Computer Science +15

A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

Young-Ho Kwak, Inhwa Jung, Hyungdong Lee et al. · 2007 · 24 citations

Engineering, Electrical Engineering, Low-power Design +11

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology

Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi et al. · IEEE Journal of Solid-State Circuits · 2011 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17

Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface

Dongsuk Shin, Kwang-Jin Na, Daehan Kwon et al. · 2009 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +16

A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

Hyun-Woo Lee, Won-Joo Yun, Sin-deok Kang et al. · 2005 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17