Modeling the subthreshold swing in MOSFET's

E.P. Vandamme, P. Jansen, L. Deferm

IEEE Electron Device Letters

Device ModelingElectrical EngineeringSemiconductor DeviceEngineeringPhysics +10

CMOS compatible wafer scale adhesive bonding for circuit transfer

S. van der Green, M. Rosmeulen, P. Jansen, +2

Scale Adhesive BondingElectrical EngineeringCircuit TransferEngineeringAdvanced Packaging (Semiconductors) +9

Lithography Options for the 32 nm Half Pitch Node and Beyond

Kurt Ronse, P. Jansen, Roel Gronheid, +6

IEEE Transactions on Circuits and Systems I Regular Papers

Optical MaterialsEngineeringElectron-beam LithographyMicroscopyWafer Scale Processing +17

Substrate bonding techniques for CMOS processed wafers

Sonja van der Groen, M. Rosmeulen, Kris Baert, +2

Journal of Micromechanics and Microengineering

Electrical EngineeringCircuit TransferEngineeringAdvanced Packaging (Semiconductors)Flexible Electronics +12

Practicalities and limitations of scanning capacitance microscopy for routine integrated circuit characterization

R. J. Stephenson, Peter Wolf, Thomas Trenkler, +4

Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena

EngineeringMicroscopyDc BiasDrain ArchitecturesIntegrated Circuits +18

New aspects of nanopotentiometry for complementary metal–oxide–semiconductor transistors

Thomas Trenkler, R. J. Stephenson, P. Jansen, +2

Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena

EngineeringNew AspectsOptoelectronic DevicesSemiconductor DeviceSemiconductor Nanostructures +16

Precision electrical trimming of very low TCR poly-SiGe resistors

J.A. Babcock, P. Francis, Rashid Bashir, +12

IEEE Electron Device Letters

Materials ScienceElectrical EngineeringEngineeringResistorSpecific Resistance +11

Improving the ESD self-protection capability of integrated power NLDMOS arrays

В.А. Ващенко, A. Strachan, D. Linten, +7

Electrical EngineeringEngineeringElectronic EngineeringIntegrated Power ArraysBias Temperature Instability +7

Extreme voltage and current overshoots in HV snapback devices during HBM ESD stress

D. Linten, В.А. Ващенко, Mirko Scholz, +7

Nominal HbmElectrical EngineeringEngineeringExtreme VoltageHigh Voltage Engineering +6

SCCF — System to component level correlation factor

S. Thijs, Mirko Scholz, D. Linten, +10

Electrical Overstress/Electrostatic Discharge Symposium

EngineeringIndustrial EngineeringMeasurementEducationSccf — System +19