Kurt Ronse

Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

Srikanth Samavedam, Julien Ryckaert, Eric Beyne et al. · 2020 · 109 citations

Engineering, Vlsi Design, Logic Scaling +21

EUV lithography with the Alpha Demo Tools: status and challenges

Noreen Harned, M. Goethals, Rogier Groeneveld et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007 · 49 citations

Engineering, Electron-beam Lithography, Target Fabrication +16

Influence of gate patterning on line edge roughness

Leonardus H. A. Leunissen, R. Jonckheere, Kurt Ronse et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 2003 · 38 citations

Electrical Engineering, Physical Design (Electronics), Engineering +9

Metrology method for the correlation of line edge roughness for different resists before and after etch

Stephanie Winkelmeier, Marko Sarstedt, M. Ereken et al. · Microelectronic Engineering · 2001 · 35 citations

Different Resists, Engineering, Measurement +4

Maintaining Moore’s law: enabling cost-friendly dimensional scaling

Arindam Mallik, Julien Ryckaert, A. Mercha et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2015 · 33 citations