Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

Abstract

With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews the latest trends and advances in technology to enable logic scaling. Dimensional scaling, enabled by EUV lithography, will continue with advances in multi-patterning. Higher costs of EUV multi-patterning will be mitigated by high (0.55) numerical aperture (NA) EUV simplifying the patterning and potentially leading to higher yield. Logic standard cell scaling below 6-track (6T) with adequate drive current per footprint will require adoption of Gate-All-Around (GAA) device architectures, like nanosheets, along with scaling boosters like buried power rails (BPR) and semi-damascene metal integration scheme with air-gaps. Scaling below 5-track (5T) will require new compact device architectures like complementary FETs (CFETs) and alternate intra-cell interconnect layouts. Slowing SRAM scaling can also benefit from migration to BPR, forksheets and CFETs. Channels formed from 2D materials can theoretically enable gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) and contacted poly pitch (CPP) scaling. Several new material innovations will be needed to enable 2D atomic channel transistors. Changing our view from circuits to systems, 3D integration techniques will continue to enable subsystem scaling like cache partitioning of SoCs to improve memory access. Finally, a methodology to estimate the environmental impact of technology scaling choices is proposed.