M. H. Na

Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

Srikanth Samavedam, Julien Ryckaert, Eric Beyne et al. · 2020 · 113 citations

Engineering, Computer Engineering, Electrical Engineering +17

Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!

Julien Ryckaert, M. H. Na, Pieter Weckx et al. · 2019 · 84 citations

Engineering, Computer Engineering, Electrical Engineering +17

Introducing 2D-FETs in Device Scaling Roadmap using DTCO

Zubair Ahmed, Aryan Afzalian, T. Schram et al. · 2020 · 47 citations

Engineering, Computer Engineering, Electrical Engineering +16

Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck

Zs. Tôkei, V. Vega, Gayle Murdoch et al. · 2020 · 30 citations

Engineering, Electrical Engineering, Materials Engineering +16

IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge

D. Saito, Jonas Doevenspeck, Stefan Cosemans et al. · IEEE Transactions on Electron Devices · 2020 · 28 citations

Engineering, Computer Engineering, Electrical Engineering +15