Practicalities and limitations of scanning capacitance microscopy for routine integrated circuit characterization

Abstract

We have imaged several n-type metal-oxide-semiconductor transistors with different source and drain architectures to assess the feasibility of extracting useful figures of merit, such as the effective channel length of a device, from the data. By varying the dc bias on the sample we observe a shift of the junction position in the image and consider how best to interpret a set of voltage dependent images produced for a single sample. Careful attention is paid to the effects of surface variation from sample preparation and tip wear during an experiment by considering the scanning capacitance microscopy signal in the substrate as a function of applied dc bias.