Mark I. Gardner

High-k gate stacks for planar, scaled CMOS integrated circuits

Howard R. Huff, C. Lim, Y. Kim et al. · Microelectronic Engineering · 2003 · 63 citations

Engineering, Computer Engineering, Electrical Engineering +12

Dual high-/spl kappa/ gate dielectric with poly gate electrode: HfSiON on nMOS and Al/sub 2/O/sub 3/ capping layer on pMOS

Hong-Jyh Li, Mark I. Gardner · IEEE Electron Device Letters · 2005 · 42 citations

Engineering, Electrical Engineering, Materials Engineering +16

Subnanometer Scaling of HfO[sub 2]/Metal Electrode Gate Stacks

Jeff J. Peterson, Chadwin D. Young, Joel Barnett et al. · Electrochemical and Solid-State Letters · 2004 · 23 citations · Full text

Engineering, Electrical Engineering, Materials Science +17

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Xuguang Wang, Jeff J. Peterson, P. Majhi et al. · IEEE Electron Device Letters · 2005 · 19 citations

Engineering, Electrical Engineering, Materials Science +17

Integration of high-k gate stack systems into planar CMOS process flows

Howard R. Huff, Avinash Kumar Ágarwal, Y. Kim et al. · 2002 · 14 citations

Engineering, Electrical Engineering, Materials Engineering +17